| NMI Disable |
NMI interrupt line to the CPU is disabled by setting bit 7 I?O port 70h (CMOS) |
| Power On Delay |
Once the keyboard controller gets power, it sets the hard and soft reset bits. Check the keyboard controller or clock generator if a failure occurs |
| Initialize Chipsets |
Check the BIOS, CLOCK and chipsets |
| Reset Determination |
The BIOS reads the bits in the keyboard controller to see if a hard or soft reset is required (a soft reset will not test memory above 64K). Failure could be the BIOS or keyboard controller |
| ROM BIOS Checksum |
The BIOS performs a checksum on itself and adds a preset factory value that should make it equal to 00. If a failure occurs, check the BIOS chips |
| Keyboard Test |
A command is sent to the 8042 keyboard controller which performs a test and sets a buffer space for commands. After the buffer is defined the BIOS sends a command byte, writes data to the buffer, checks the high order bits of the internal keyboard controller and issues a No Operation (NOP) command |
| CMOS |
Shutdown byte in CMOS RAM offset 0F is tested, the BIOS checksum calculated and diagnostic byte 0E updated before the CMOS RAM area is initialized and updated for date and time. Check the RTC and CMOS chip or battery if a failure occurs |
| DMA (8237) and PIC (8259) Disable |
The DMA and Programmable Interrupt Controller are disabled before the POST proceeds and further. Check the 8237 or 8259 chips if a failure occurs |
| Video Disable |
The video controller is disabled and port B initialized. Check the video adapter if a failure occurs |
| Chipset Initialized and Memory Detected |
Memory addressed in 64K blocks. Failure would be in the chipset. If all memory is not seen, failure could be in a chip in the block after the last one seen |
| PIT Test |
The timing functions of the 8254 Programmable Interrupt Timer are tested. The PIT and RTC chips normally cause errors here |
| Memory Refresh |
PIT's ability to refresh memory is tested. If an XT, DMA controller #1 handles this. Failure is normally the PIT (8254) in AT's or the 8237, DMA #1, in XT's |
| Address Line |
Test the address lines in the first 64K of RAM. If a failure occurs, an address line may be the problem |
| Base 64K |
Data patterns are written to the first 64K of RAM, unless there is a bad RAM chip in which case you will get a failure |
| Chipset Initialization |
The PIT, PIC and DMA controllers are initialized |
| Set Interrupt Table |
Interrupt vector table used by PIC is installed in low memory, the first 2K |
| 8042 Keyboard Controller Check |
The BIOS reads the buffer area in the keyboard controller I/O port 60. Failure here is normally the keyboard controller |
| Video Tests |
The type of video adapter is checked for, then a series of tests are performed on the adapter and monitor |
| BIOS Data Area |
The vector table is checked for proper operation and video memory verified before protected mode tests are entered into. This is done so that any errors found are displayed on the monitor |
| Protected Mode Tests |
Perform reads and writes to all memory locations below 1MB. Failure at this point indicate a bad RAM chip, the 8042 Keyboard Controller or a data line |
| DMA Chips |
The DMA registers are tested using a data pattern |
| Final Initialization |
these differ with each version. Typically, the floppy and hard drives are tested and initialized and a check is made for serial and parallel devices. The information gathered is then compared against the contents of the CMOS and you will see the results of any failures on the monitor |
| BOOT |
The BIOS hands over control to the Int 19 bootloader. This is where you would see error messages such as non-system disk |
| 01 |
NMI is disabled and the i286 register test is about to start |
| 02 |
i286 register test has passed |
| 03 |
ROM BIOS checksum test (32Kb from F8000h) passed OK |
| 04 |
8259 programmable interrupt controller has initialized OK |
| 05 |
CMOS interrupt disabled |
| 06 |
Video system disabled and the system timer checks OK |
| 07 |
8253/4 programmable-interval timer test OK |
| 08 |
Delta counter channel 2 OK |
| 09 |
Delta counter channel 1 OK |
| 0A |
Delta counter channel 0 OK |
| 0B |
Parity status cleared |
| 0C |
The refresh and system timer check OK |
| 0D |
Refresh check OK |
| 0E |
Refresh period checks OK |
| 10 |
Ready to start 64KB base memory test |
| 11 |
Address line test OK |
| 12 |
64KB base memory test OK |
| 13 |
System-interrupt vectors initialized |
| 14 |
8042 keyboard controller checks OK |
| 15 |
CMOS read/write test OK |
| 16 |
CMOS checksum and battery OK |
| 17 |
Monochrome video mode OK |
| 18 |
CGA color mode set OK |
| 19 |
Attempting to pass control to video ROM at C0000h |
| 1A |
Returned from video ROM |
| 1B |
Display memory read/write test OK |
| 1C |
Display memory read/write alternative test OK |
| 1D |
Video retrace test OK |
| 1E |
Global equipment byte set for proper video operation |
| 1F |
Ready to initialize video system |
| 20 |
Video test OK |
| 21 |
Video display OK |
| 22 |
The power-on message is displayed |
| 30 |
Ready to start the virtual-mode memory test |
| 31 |
virtual memory mode test started |
| 32 |
CPU has switched to virtual mode |
| 33 |
Testing the memory address lines |
| 34 |
Testing the memory address lines |
| 35 |
Lower 1MB of RAM found |
| 36 |
Memory size computation checks OK |
| 37 |
Memory test in progress |
| 38 |
Memory below 1MB is initialized |
| 39 |
Memory above 1MB is initialized |
| 3A |
Memory size is displayed |
| 3B |
Ready to test the lower 1MB of RAM |
| 3C |
Memory test of lower 1MB OK |
| 3D |
Memory test above 1MB OK |
| 3E |
Ready to shutdown for real-mode testing |
| 3F |
Shutdown OK- now in real mode |
| 40 |
Ready to disable gate A20 |
| 41 |
A20 line disabled successfully |
| 42 |
Ready to start DMA controller test |
| 4E |
Address line test OK |
| 4F |
System still in real mode |
| 50 |
DMA page register test OK |
| 51 |
Starting DMA controller 1 register test |
| 52 |
DMA controller 1 test passed, starting DMA controller 2 register test |
| 53 |
DMA controller 2 test passed |
| 54 |
Ready to test latch on DMA controller 1 and 2 |
| 55 |
DMA controller 1 and 2 latch test OK |
| 56 |
DMA controller 1 and 2 configured OK |
| 57 |
8259 programmable interrupt controller initialized OK |
| 58 |
8259 programmable interrupt controller mask register OK |
| 59 |
Master 8259 programmable interrupt controller mask register OK |
| 5A |
Ready to check timer interrupts |
| 5B |
Timer interrupt check OK |
| 5C |
Ready to test keyboard interrupt |
| 5D |
Error detected in timer or keyboard interrupt |
| 5E |
8259 programmable interrupt controller error |
| 5F |
8259 programmable interrupt controller OK |
| 70 |
Start of keyboard test |
| 71 |
Keyboard controller Ok |
| 72 |
Keyboard tested OK |
| 73 |
Keyboard global initialization OK |
| 74 |
Floppy setup ready to start |
| 75 |
Floppy controller setup OK |
| 76 |
Hard disk setup ready to start |
| 77 |
Hard disk controller setup OK |
| 79 |
Ready to initialize timer data |
| 7A |
Verifying CMOS battery power |
| 7B |
CMOS battery verified OK |
| 7D |
Analyzing CMOS RAM size |
| 7E |
CMOS memory size updated |
| 7F |
Send control to adapter ROM |
| 80 |
Enable the setup routine if <Delete> is pressed |
| 82 |
Printer data initialization is OK |
| 83 |
RS-232 data initialization is OK |
| 84 |
80x87 check and test OK |
| 85 |
Display any soft-error message |
| 86 |
Give control to ROM E0000h |
| 87 |
Return from system ROM |
| 00 |
Call the Int19 boot loader |